Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date         : Mon Apr 20 17:23:16 2026
| Host         : debian running 64-bit Debian GNU/Linux 13 (trixie)
| Command      : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt
| Design       : system_wrapper
| Device       : 7z020-clg400
| Speed File   : -1  PRODUCTION 1.12 2019-11-22
| Design State : Routed
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Clock Utilization Report

Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Device Cell Placement Summary for Global Clock g1
8. Device Cell Placement Summary for Global Clock g2
9. Device Cell Placement Summary for Global Clock g3
10. Clock Region Cell Placement per Global Clock: Region X0Y0
11. Clock Region Cell Placement per Global Clock: Region X1Y0
12. Clock Region Cell Placement per Global Clock: Region X0Y1
13. Clock Region Cell Placement per Global Clock: Region X1Y1
14. Clock Region Cell Placement per Global Clock: Region X0Y2
15. Clock Region Cell Placement per Global Clock: Region X1Y2

1. Clock Primitive Utilization
------------------------------

+----------+------+-----------+-----+--------------+--------+
| Type     | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL |    4 |        32 |   0 |            0 |      0 |
| BUFH     |    0 |        72 |   0 |            0 |      0 |
| BUFIO    |    0 |        16 |   0 |            0 |      0 |
| BUFMR    |    0 |         8 |   0 |            0 |      0 |
| BUFR     |    0 |        16 |   0 |            0 |      0 |
| MMCM     |    0 |         4 |   0 |            0 |      0 |
| PLL      |    1 |         4 |   0 |            0 |      0 |
+----------+------+-----------+-----+--------------+--------+


2. Global Clock Resources
-------------------------

+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------------------+-----------------------------------+-------------------------------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site           | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock                   | Driver Pin                        | Net                                             |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------------------+-----------------------------------+-------------------------------------------------+
| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y16 | n/a          |                 6 |       22482 |               0 |        8.138 | clk_out1_system_pll_0_0 | system_i/pll_0/inst/clkout1_buf/O | system_i/pll_0/inst/clk_out1                    |
| g1        | src1      | BUFG/O          | None       | BUFGCTRL_X0Y17 | n/a          |                 1 |           1 |               0 |        4.069 | clk_out2_system_pll_0_0 | system_i/pll_0/inst/clkout2_buf/O | system_i/pll_0/inst/clk_out2                    |
| g2        | src2      | BUFG/O          | None       | BUFGCTRL_X0Y18 | n/a          |                 1 |           1 |               0 |        4.069 | clk_out3_system_pll_0_0 | system_i/pll_0/inst/clkout3_buf/O | system_i/pll_0/inst/clk_out3                    |
| g3        | src3      | BUFG/O          | None       | BUFGCTRL_X0Y19 | n/a          |                 1 |           1 |               0 |        8.138 | clkfbout_system_pll_0_0 | system_i/pll_0/inst/clkf_buf/O    | system_i/pll_0/inst/clkfbout_buf_system_pll_0_0 |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------------------+-----------------------------------+-------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)


3. Global Clock Source Details
------------------------------

+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+-------------------------+---------------------------------------------+---------------------------------------------+
| Source Id | Global Id | Driver Type/Pin    | Constraint | Site           | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock            | Driver Pin                                  | Net                                         |
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+-------------------------+---------------------------------------------+---------------------------------------------+
| src0      | g0        | PLLE2_ADV/CLKOUT0  | None       | PLLE2_ADV_X1Y1 | X1Y1         |           1 |               0 |               8.138 | clk_out1_system_pll_0_0 | system_i/pll_0/inst/plle2_adv_inst/CLKOUT0  | system_i/pll_0/inst/clk_out1_system_pll_0_0 |
| src1      | g1        | PLLE2_ADV/CLKOUT1  | None       | PLLE2_ADV_X1Y1 | X1Y1         |           1 |               0 |               4.069 | clk_out2_system_pll_0_0 | system_i/pll_0/inst/plle2_adv_inst/CLKOUT1  | system_i/pll_0/inst/clk_out2_system_pll_0_0 |
| src2      | g2        | PLLE2_ADV/CLKOUT2  | None       | PLLE2_ADV_X1Y1 | X1Y1         |           1 |               0 |               4.069 | clk_out3_system_pll_0_0 | system_i/pll_0/inst/plle2_adv_inst/CLKOUT2  | system_i/pll_0/inst/clk_out3_system_pll_0_0 |
| src3      | g3        | PLLE2_ADV/CLKFBOUT | None       | PLLE2_ADV_X1Y1 | X1Y1         |           1 |               0 |               8.138 | clkfbout_system_pll_0_0 | system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT | system_i/pll_0/inst/clkfbout_system_pll_0_0 |
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+-------------------------+---------------------------------------------+---------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)


4. Clock Regions: Key Resource Utilization
------------------------------------------

+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 4432 |  2500 | 3139 |  1000 |    0 |    60 |    2 |    30 |   47 |    60 |
| X1Y0              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  280 |  3200 |  133 |   850 |    0 |    60 |    1 |    30 |   10 |    40 |
| X0Y1              |    1 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 | 4276 |  1200 | 2009 |   400 |    0 |    20 |    1 |    10 |   19 |    20 |
| X1Y1              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    1 |     1 |    0 |     0 |    0 |     0 |   32 |    50 |    0 |    50 | 7604 |  2600 | 3093 |   850 |    0 |    60 |    1 |    30 |   33 |    40 |
| X0Y2              |    1 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 | 1156 |  1200 |  708 |   400 |    0 |    20 |    1 |    10 |   10 |    20 |
| X1Y2              |    3 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |   18 |    50 | 1252 |  2600 |  753 |   850 |    0 |    60 |    0 |    30 |   23 |    40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts


5. Clock Regions : Global Clock Summary
---------------------------------------

All Modules
+----+----+----+
|    | X0 | X1 |
+----+----+----+
| Y2 |  1 |  3 |
| Y1 |  1 |  2 |
| Y0 |  1 |  1 |
+----+----+----+


6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------

+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock                   | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                          |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
| g0        | BUFG/O          | n/a               | clk_out1_system_pll_0_0 |       8.138 | {0.000 4.069} |       22346 |        0 |              0 |        0 | system_i/pll_0/inst/clk_out1 |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+-------+-------+-----------------------+
|    | X0    | X1    | HORIZONTAL PROG DELAY |
+----+-------+-------+-----------------------+
| Y2 |  1459 |  1627 |                     0 |
| Y1 |  5002 |  8310 |                     0 |
| Y0 |  5648 |   300 |                     0 |
+----+-------+-------+-----------------------+


7. Device Cell Placement Summary for Global Clock g1
----------------------------------------------------

+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock                   | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                          |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
| g1        | BUFG/O          | n/a               | clk_out2_system_pll_0_0 |       4.069 | {1.780 3.815} |           1 |        0 |              0 |        0 | system_i/pll_0/inst/clk_out2 |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+----+----+-----------------------+
|    | X0 | X1 | HORIZONTAL PROG DELAY |
+----+----+----+-----------------------+
| Y2 |  0 |  1 |                     0 |
| Y1 |  0 |  0 |                     - |
| Y0 |  0 |  0 |                     - |
+----+----+----+-----------------------+


8. Device Cell Placement Summary for Global Clock g2
----------------------------------------------------

+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock                   | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                          |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
| g2        | BUFG/O          | n/a               | clk_out3_system_pll_0_0 |       4.069 | {2.289 4.323} |           1 |        0 |              0 |        0 | system_i/pll_0/inst/clk_out3 |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+----+----+-----------------------+
|    | X0 | X1 | HORIZONTAL PROG DELAY |
+----+----+----+-----------------------+
| Y2 |  0 |  1 |                     0 |
| Y1 |  0 |  0 |                     - |
| Y0 |  0 |  0 |                     - |
+----+----+----+-----------------------+


9. Device Cell Placement Summary for Global Clock g3
----------------------------------------------------

+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock                   | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                             |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------+
| g3        | BUFG/O          | n/a               | clkfbout_system_pll_0_0 |       8.138 | {0.000 4.069} |           0 |        0 |              1 |        0 | system_i/pll_0/inst/clkfbout_buf_system_pll_0_0 |
+-----------+-----------------+-------------------+-------------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+----+----+-----------------------+
|    | X0 | X1 | HORIZONTAL PROG DELAY |
+----+----+----+-----------------------+
| Y2 |  0 |  0 |                     - |
| Y1 |  0 |  1 |                     0 |
| Y0 |  0 |  0 |                     - |
+----+----+----+-----------------------+


10. Clock Region Cell Placement per Global Clock: Region X0Y0
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                          |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| g0        | n/a   | BUFG/O          | None       |        5648 |               0 | 4432 |        1167 |    2 |  47 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


11. Clock Region Cell Placement per Global Clock: Region X1Y0
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                          |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+------------------------------+
| g0        | n/a   | BUFG/O          | None       |         300 |               0 | 280 |           8 |    1 |  10 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


12. Clock Region Cell Placement per Global Clock: Region X0Y1
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                          |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| g0        | n/a   | BUFG/O          | None       |        5002 |               0 | 4276 |         706 |    1 |  19 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


13. Clock Region Cell Placement per Global Clock: Region X1Y1
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                             |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------+
| g0        | n/a   | BUFG/O          | None       |        8310 |               0 | 7604 |         671 |    1 |  33 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out1                    |
| g3        | n/a   | BUFG/O          | None       |           1 |               0 |    0 |           0 |    0 |   0 |  0 |    0 |   1 |       0 | system_i/pll_0/inst/clkfbout_buf_system_pll_0_0 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


14. Clock Region Cell Placement per Global Clock: Region X0Y2
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                          |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| g0        | n/a   | BUFG/O          | None       |        1459 |               0 | 1156 |         291 |    1 |  10 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


15. Clock Region Cell Placement per Global Clock: Region X1Y2
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                          |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
| g0        | n/a   | BUFG/O          | None       |        1627 |               0 | 1252 |         336 |    0 |  23 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out1 |
| g1        | n/a   | BUFG/O          | None       |           1 |               0 |    0 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out2 |
| g2        | n/a   | BUFG/O          | None       |           1 |               0 |    0 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | system_i/pll_0/inst/clk_out3 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts



# Location of BUFG Primitives 
set_property LOC BUFGCTRL_X0Y19 [get_cells system_i/pll_0/inst/clkf_buf]
set_property LOC BUFGCTRL_X0Y18 [get_cells system_i/pll_0/inst/clkout3_buf]
set_property LOC BUFGCTRL_X0Y17 [get_cells system_i/pll_0/inst/clkout2_buf]
set_property LOC BUFGCTRL_X0Y16 [get_cells system_i/pll_0/inst/clkout1_buf]

# Location of IO Primitives which is load of clock spine

# Location of clock ports
set_property LOC IOB_X1Y75 [get_ports adc_clk_n_i]
set_property LOC IOB_X1Y76 [get_ports adc_clk_p_i]

# Clock net "system_i/pll_0/inst/clk_out3" driven by instance "system_i/pll_0/inst/clkout3_buf" located at site "BUFGCTRL_X0Y18"
#startgroup
create_pblock {CLKAG_system_i/pll_0/inst/clk_out3}
add_cells_to_pblock [get_pblocks  {CLKAG_system_i/pll_0/inst/clk_out3}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="system_i/pll_0/inst/clk_out3"}]]]
resize_pblock [get_pblocks {CLKAG_system_i/pll_0/inst/clk_out3}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "system_i/pll_0/inst/clk_out2" driven by instance "system_i/pll_0/inst/clkout2_buf" located at site "BUFGCTRL_X0Y17"
#startgroup
create_pblock {CLKAG_system_i/pll_0/inst/clk_out2}
add_cells_to_pblock [get_pblocks  {CLKAG_system_i/pll_0/inst/clk_out2}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="system_i/pll_0/inst/clk_out2"}]]]
resize_pblock [get_pblocks {CLKAG_system_i/pll_0/inst/clk_out2}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "system_i/pll_0/inst/clk_out1" driven by instance "system_i/pll_0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock {CLKAG_system_i/pll_0/inst/clk_out1}
add_cells_to_pblock [get_pblocks  {CLKAG_system_i/pll_0/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="system_i/pll_0/inst/clk_out1"}]]]
resize_pblock [get_pblocks {CLKAG_system_i/pll_0/inst/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup
