Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date             : Mon Apr 13 14:58:27 2026
| Host             : debian running 64-bit Debian GNU/Linux 13 (trixie)
| Command          : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
| Design           : system_wrapper
| Device           : xc7z020clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 2.093        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 1.935        |
| Device Static (W)        | 0.157        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 60.9         |
| Junction Temperature (C) | 49.1         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.051 |        8 |       --- |             --- |
| Slice Logic              |     0.020 |    22357 |       --- |             --- |
|   LUT as Logic           |     0.015 |     4203 |     53200 |            7.90 |
|   CARRY4                 |     0.002 |      703 |     13300 |            5.29 |
|   Register               |     0.002 |    11924 |    106400 |           11.21 |
|   LUT as Shift Register  |    <0.001 |     1336 |     17400 |            7.68 |
|   LUT as Distributed RAM |    <0.001 |       64 |     17400 |            0.37 |
|   Others                 |     0.000 |     1609 |       --- |             --- |
| Signals                  |     0.040 |    18350 |       --- |             --- |
| Block RAM                |     0.024 |        6 |       140 |            4.29 |
| PLL                      |     0.104 |        1 |         4 |           25.00 |
| DSPs                     |     0.079 |       92 |       220 |           41.82 |
| I/O                      |     0.340 |       61 |       125 |           48.80 |
| PS7                      |     1.277 |        1 |       --- |             --- |
| Static Power             |     0.157 |          |           |                 |
| Total                    |     2.093 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.243 |       0.225 |      0.018 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.075 |       0.058 |      0.017 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.100 |       0.099 |      0.001 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.003 |       0.002 |      0.002 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccpint   |       1.000 |     0.701 |       0.666 |      0.035 |       NA    | Unspecified | NA         |
| Vccpaux   |       1.800 |     0.037 |       0.027 |      0.010 |       NA    | Unspecified | NA         |
| Vccpll    |       1.800 |     0.017 |       0.014 |      0.003 |       NA    | Unspecified | NA         |
| Vcco_ddr  |       1.500 |     0.356 |       0.354 |      0.002 |       NA    | Unspecified | NA         |
| Vcco_mio0 |       3.300 |     0.001 |       0.000 |      0.001 |       NA    | Unspecified | NA         |
| Vcco_mio1 |       2.500 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+-------------------------+---------------------------------------------+-----------------+
| Clock                   | Domain                                      | Constraint (ns) |
+-------------------------+---------------------------------------------+-----------------+
| adc_clk_p_i             | adc_clk_p_i                                 |             8.1 |
| clk_out1_system_pll_0_0 | system_i/pll_0/inst/clk_out1_system_pll_0_0 |             8.1 |
| clk_out2_system_pll_0_0 | system_i/pll_0/inst/clk_out2_system_pll_0_0 |             4.1 |
| clk_out3_system_pll_0_0 | system_i/pll_0/inst/clk_out3_system_pll_0_0 |             4.1 |
| clkfbout_system_pll_0_0 | system_i/pll_0/inst/clkfbout_system_pll_0_0 |             8.1 |
+-------------------------+---------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+------------------------+-----------+
| Name                   | Power (W) |
+------------------------+-----------+
| system_wrapper         |     1.935 |
|   system_i             |     1.603 |
|     cic_0              |     0.015 |
|       U0               |     0.015 |
|     cic_1              |     0.016 |
|       U0               |     0.016 |
|     dac_0              |     0.006 |
|       inst             |     0.006 |
|     dds_0              |     0.018 |
|       inst             |     0.018 |
|     dds_2              |     0.015 |
|       inst             |     0.015 |
|     dds_3              |     0.015 |
|       inst             |     0.015 |
|     fir_0              |     0.114 |
|       U0               |     0.114 |
|     fsk_detector_tap_0 |     0.001 |
|       inst             |     0.001 |
|     gpio_deb           |     0.001 |
|       inst             |     0.001 |
|     hub_0              |     0.004 |
|       inst             |     0.004 |
|     io_bridge_out      |     0.006 |
|       inst             |     0.006 |
|     mult_0             |     0.001 |
|       inst             |     0.001 |
|     mult_1             |     0.001 |
|       inst             |     0.001 |
|     mult_4             |     0.001 |
|       inst             |     0.001 |
|     mult_5             |     0.001 |
|       inst             |     0.001 |
|     pll_0              |     0.105 |
|       inst             |     0.105 |
|     ps_0               |     1.277 |
|       inst             |     1.277 |
|     writer_0           |     0.002 |
|       inst             |     0.002 |
+------------------------+-----------+


